1. Field of the Invention
The present invention relates generally to dual damascene semiconductor manufacturing processes, and more particularly, to methods and systems for planarizing features and layers in a semiconductor manufacturing process.
2. Description of the Related Art
Dual damascene manufacturing processes are becoming more common in semiconductor manufacturing. In a typical dual damascene manufacturing process, one or more conductive materials are deposited in previously patterned trenches and vias formed in a semiconductor substrate or films formed on the semiconductor substrate to form the desired electrical circuit interconnects. An excess or overburden portion of the conductive material is often formed. The overburden portion of the conductive material is unnecessary and undesirable and must be removed both to produce a damascene feature and to provide a planar surface for subsequent processing. Often, the overburden portion is formed unevenly having low areas and raised areas that correspond to the patterned trenches and vias formed in the underlying layer.
The overburden portion of the conductive material is typically removed from the semiconductor substrate through chemical mechanical polishing (CMP) and electro-chemical polishing (ECP) (e.g., etching) processes and combinations of CMP and ECP processes. Each of these processes has significant shortfalls. By way of example, ECP typically has a relatively low throughput, poor uniformity and inability to effectively remove non-conductive material.
CMP is a physical contact process which typically leaves conductive residues, or causes corrosion of the various materials, or result in non-uniform removal, and the inability to suitably planarize interconnect and interlevel dielectric (ILD) top surface. CMP can also cause stress related damage (e.g., interlayer delamination, peeling) to remaining interconnect and ILD structures. The CMP-caused stress damage is further exacerbated by the very poor inter-layer adhesion characteristics of the more-recently used materials (e.g., low-k dielectric materials). Reducing the physical force of the CMP process to reduce the physical stress can often result in unacceptably low throughput rates and other poor process performance parameters.
FIG. 1A shows a typical semiconductor substrate 100. A typical CMP process has been applied to the semiconductor substrate 100 to substantially remove an overburden layer and to expose an underlying layer 104. Layer 104 includes features (e.g., vias, trenches, etc.) that were formed in a previous manufacturing process. A portion of the overburden layer remains in the form of a non-uniformity 102 on the surface of the semiconductor substrate 100. The non-uniformity 102 has a thickness of greater than about 500 angstroms in a thickest portion. Multiple elevations 102A–102E of the non-uniformity 102 are illustrated. By way of example, the region encompassed by elevation 102A can represent where the non-uniformity 102 has a thickness of about less than 100 angstroms. Similarly, the region encompassed by elevation 102B can represent where the non-uniformity 102 has a thickness of between about 100 and about 200 angstroms. The region encompassed by elevation 102C can represent where the non-uniformity 102 has a thickness of between about 200 and about 300 angstroms. The region encompassed by elevation 102D can represent where the non-uniformity 102 has a thickness of between about 300 and about 400 angstroms. The region encompassed by elevation 102E can represent where the non-uniformity 102 has a thickness of between about 400 and about 500 angstroms. The region encompassed by elevation 102F can represent where the non-uniformity 102 has a thickness of greater than about 500 angstroms.
The typical CMP process includes applying a moving a polishing pad to the surface of the semiconductor substrate 100. Friction is generated between the polishing pad and the materials in surface of the semiconductor substrate 100. The friction removes a portion of the materials in the surface of the semiconductor substrate 100. Each material on the surface of the semiconductor substrate 100 has a different coefficient of friction with the polishing pad. By way of example, the surface of the semiconductor substrate 100 can include oxide (e.g., silicon oxide) and copper materials. The oxide has a first coefficient of friction with the polishing pad and the copper has a second coefficient of friction with the polishing pad. The first coefficient of friction is typically different (i.e., higher or lower) than the second coefficient of friction.
Where a difference in the first and second coefficients of friction occur, stresses can be imparted into the semiconductor substrate 100. At a point or area where the two different coefficients of friction meet, the stresses can be substantially concentrated. By way of example, as a typical CMP process polishes through a copper layer to expose an underlying oxide layer, the stresses become concentrated at the areas where the differences in coefficients of friction occur (i.e., where the copper layer and the oxide layers meet).
Referring again to FIG. 1A above, as the polishing pad polishes across a first material (i.e., the exposed underlying layer 104) to a second material (i.e., the non-uniformity 102) the coefficient of friction varies. As a result, the polishing process can concentrate considerable stresses into the semiconductor substrate 100 where the non-uniformity is thinnest (e.g., region 102A). Region 102A can have relatively large areas. As a result, the stresses can be imparted to a relatively large portion of the semiconductor substrate 100. These stresses can be substantially parallel (i.e., horizontal) stress vectors that are substantially parallel with the surface of the substrate 100. These stresses can also be substantially vertical stress vectors that are substantially perpendicular with the surface of the semiconductor substrate 100.
FIG. 1B shows a detailed, cross-sectional view of the semiconductor substrate 100. As shown in FIG. 1A, the non-uniformity 102 becomes relatively thin (e.g., toward the outer edges) such as in region 102A, the non-uniformity becomes increasing susceptible to damage caused by the vertical and horizontal stresses. By way of example, if the polishing pad is moving in the direction 120 relative to the surface of the substrate, then the thin, edge region 102A of the non-uniformity 102 can be peeled away from the underlying layer 104 by the horizontal stresses caused by the difference in a first coefficient of friction between the underlying layer 104 and the polishing pad and a second coefficient of friction between the non-uniformity 102 and the polishing pad. As the non-uniformity 102 is pulled away from the underlying layer 104, a feature 112 that is attached to the non-uniformity 102 can be pulled or stressed in a vertical direction. By way of example, the feature 112 can be a via that is filled with a conductive material (e.g., copper, aluminum, etc) to provide a contact to a device 114 in an underlying layer 116. As the conductive material is pulled vertically from the via 112, the contact area with the device 114 is substantially reduced.
FIG. 1C shows yet another example of damage 132 that can be caused by typical CMP processes. Due to the difference between the first coefficient of friction (e.g., between the layer 104 and the polishing pad) and a third coefficient of friction between the conductive material in the via 112, the layer 104 can be pulled away from the conductive material in the via 112. FIG. 1D shows another detailed view of the damage 132 that can be caused by typical CMP processes. As shown in FIG. 1D, the conductive material in the via 112 is slightly dished, relative to the layer 104. As a result, an edge 134 of the layer 104 is exposed. The edge 134 can further concentrate the stresses on the edge so as to cause the edge of the layer 104 to be pulled away from the conductive material in the via 112.
As a result of the layer 104 being pulled away from the conductive material in the via 112, a void 132 is formed between the conductive material in the via 112 and the layer 104. The void 132 can cause countless problems (e.g., corrosion, misalignment, etc.) in the subsequent manufacturing processes. The void 132 can also substantially reduce the reliability of the contact to the device 114. As shown in FIGS. 1A–C above, the stresses imparted to the top layers 102 and 104 by the typical CMP processes can damage features 112, 114 one or more layers below.
In view of the foregoing, there is a need for an improved planarizing system and method to uniformly and substantially remove overburden material while minimizing physical stresses to the remaining features. The improved planarizing system and method should be suitable for use in semiconductor manufacturing and should be applicable to processes such as a dual damascene process or other semiconductor manufacturing processes.